1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to rail-to-rail operational amplifier circuits.
2. Description of the Related Art
Classical operational amplifiers (OP AMPs) are well known versatile electronic devices that are used in designing many types of electronic circuits. By way of example, when the terminals of a classical OP AMP are electrically interconnected with other components, the OP AMP may be used to make differentiating circuits, integrating circuits, gain-up circuits, gain-down circuits, etc. Typically, classical OP AMPs are powered-up with a negative power supply voltage (i.e., -5 V) and an upper rail power supply voltage (e.g., +5 V). In operation, a signal input voltage having a dominant common mode voltage and a differential voltage is typically input at the positive terminal of the classical OP AMP. In the classical OP AMP, the positive terminal (as well as the negative node) is typically connected to an internal single input transistor pair.
In this manner, the signal input voltage may range somewhere between the negative power supply voltage and the positive power supply voltage. In addition, the classical OP AMP has a pair of output transistors that typically have their sources (or emitters) tied together at an output node. In this manner, the output node of the classical OP AMP will be capable of producing output signals ranging from 1 volt to 2 volts above the negative power supply voltage and from 1 volt to 2 volts below the positive power supply voltage.
Although classical OP AMPs work well for circuits that only require operation between a negative power supply voltage and a positive power supply voltage, many circuits now demand that operational amplifiers provide rail-to-rail inputs and outputs. For example, rail-to-rail OP AMPs are ideally designed to receive signal input voltages ranging between the negative power supply and the positive power supply, including both. Circuit designers were therefore forced to modify the classical OP AMP design to enable inputs ranging between the negative rail and the positive rail, as well as providing outputs ranging between the same negative and positive rails. Unfortunately, current rail-to-rail circuit designs fall short of delivering "true" rail-to-rail performance.
FIG. 1A shows a conventional rail-to-rail OP AMP 10 that uses a cross-over circuit 20 to achieve input signal swings from rail-to-rail. In this example, "V" represents a positive rail, and "G" represents a negative rail. Conventional rail-to-rail OP AMP 10 is shown having an NPN differential pair 12 that is used for input voltages near a positive rail. NPN differential pair 12 generally includes an NPN transistor 28 and an NPN transistor 30 having their respective emitters coupled to a node that leads to cross-over circuit 20. Also shown is a PNP differential pair 14 that includes a PNP transistor 32 and a PNP transistor 34 that are used for input voltages near a negative rail. In this example, the emitters of PNP transistors 32 and 34 are shown coupled to cross-over circuit 20. The base terminals of NPN transistor 30 and PNP transistor 34 are coupled to a positive terminal 16, and the base terminals of NPN transistor 28 and PNP transistor 32 are coupled to a negative terminal 15.
The collector terminals of NPN differential pair 12 and PNP differential pair 14 are shown coupled to a folded cascode circuit 18. In general, folded cascode circuit 18 is used for combining output signals received from differential pairs 12 and 14, and for outputting the combined signals to an output stage 40. As shown, folded cascode circuit 18 and output stage 40 are coupled to a positive voltage supply (V) and a negative voltage supply (G). As described above, "G" represents a negative rail voltage, and "V" represents a positive rail voltage. Output stage 40 typically includes a PNP transistor 52 and an NPN 54 that are electrically coupled to a level shifter 56 at their base terminals. In general, when output stage 40 receives a HIGH, PNP transistor 52 is turned off and NPN transistor 54 is turned on. Conversely, when output stage 40 receives a LOW, NPN transistor 54 is turned off and PNP transistor 52 is turned on. Accordingly, the output is passed out through a common collector. As will be described below, the common collector output arrangement has the drawback that performance is strongly affected by the load. Thus, bandwidth, and stability tend to be affected by output loading.
FIG. 1B is a current and voltage plot illustrating the response of a current I.sub.1 and a current I.sub.2 of FIG. 1A with respect to signal input voltage. Because most signal input voltages tend to utilize the negative voltage levels and lower-positive voltage levels, cross-over circuit 20 is often configured to transition between current I.sub.1 and I.sub.2 at a transition location 62 that is about 1 volt away from a positive voltage supply (V). That is, current I.sub.2 will be ON (i.e., PNP differential pair 14 is active) for signal input voltages ranging between the negative voltage supply (G) and up to the end of a cross-over range (V.sub.CO). Conversely, current I.sub.1 will be ON (i.e., NPN differential pair 12 is active) from the positive voltage supply (V) and down to the other end of the cross-over range (V.sub.CO).
Although conventional rail-to-rail OP AMP 10 is capable of producing swings between positive and negative voltages, various errors are introduced which unfortunately handicap its rail-to-rail performance. It is important to realize that the input of conventional rail-to-rail OP AMP 10 is usually operating while either NPN differential pair 12 or PNP differential pair 14 is ON (except in V.sub.CO, where both are ON). Unfortunately, the differential output current from differential pair 12 and the differential output current from PNP differential pair 14 have a tendency to vary due to well known voltage offset errors.
Because one transistor is rarely identical to another, the base-emitter voltages (V.sub.BE) of NPN transistors 28 and 30 will likewise rarely match. Accordingly, the difference between the base-emitter voltage (V.sub.BE) of NPN transistors 28 and 30 define an input offset voltage. The input offset voltage of NPN differential pair 12 will therefore produce an error current I.sub.01 (i.e., leading to folded cascode circuit 18) that takes into account the resulting offset voltage. Even if the offset errors are reduced (i.e., by trimming or the like) for NPN differential pair 12, PNP differential pair 14 will also have its associated offset voltage that produces its own unique current I.sub.02 (i.e., leading to folded cascode circuit 18). Although the difference between currents I.sub.01 and I.sub.02 may be small when viewed alone, at high gains, this difference is unfortunately magnified producing substantial gain nonlinearities.
The input of conventional rail-to-rail OP AMP 10 is also subject to input bias current errors. As is well known, the current gain (.beta.) of the NPN transistors 28 and 30 tends to be larger than that of the PNP transistors 32 and 34. Accordingly, because the bias current is approximately (I.sub.E /.beta.), the bias current for the NPN's will differ from the PNP's because their betas (.beta.) differ. To further complicate matters, the input bias current for NPN differential pair 12 and PNP differential pair 14 flow in opposite directions. That is, the input bias current flows into the bases for NPN transistors 28 and 30, and flows out of the bases for the PNP transistors 32 and 34. As an example, 10 nano amps may be flowing in one direction, and 20 nano amps may be flowing in the other direction. As can be appreciated, the changes in magnitude and direction of the input currents produce input bias current errors that unfortunately introduce errors at the output.
Of course, the NPN differential pair 12 and PNP differential pair 14 may be replaced with MOSFETs. When MOSFETs are used, N-channel transistors are used in place of NPN transistors 28 and 30, and P-channel transistors are used in place of PNP transistors 32 and 34. Although input bias current errors described above are insignificant, the input voltage offset errors produced by MOSFETs may be an order of magnitude greater than with bipolar transistors. In addition, it is generally well known that transition location 62 (of FIG. 1B) is substantially less uniform when MOSFETs are used. As a result, the bipolar transistors of FIG. 1A and their associated drawbacks are preferred over their MOSFET counterparts. In addition, the transconductance of the input stage tends to change during cross-over. As a result of transconductance changes, a change in bandwidth may be caused, which may lead to instability in some applications having capacitive loads.
As described above, the collectors of PNP transistor 52 and NPN transistor 54 must be tied together in order to achieve an output that swings rail-to-rail. However, the rail-to-rail swings never truly extend all the way to the positive rail and the negative rail. In optimum operation, the positive and negative rail swing is about a collector-emitter saturation voltage (V.sub.CE SAT) away. By way of example, at lower currents, V.sub.CE SAT may be as small as 0.1 volts, and at higher currents as large as 0.5 volts. Accordingly, the output swing will never be a true rail-to-rail swing. The limited rail-to-rail swing is sometimes referred to as "headroom," which refers to voltage difference between a limited rail-to-rail voltage swing and a "full-ideal" rail-to-rail voltage swing.
In addition, the common collector output stage requirement of conventional rail-to-rail OP AMP 10 suffers from being very load dependent, because the common collector output stage has a high output impedance. As a result, conventional rail-to-rail OP AMP 10 has a tendency to oscillate with capacitive loads which makes it difficult to stabilize. Further yet, more power is consumed in order to provide conventional rail-to-rail OP AMP 10 sufficient drive capacity.
In view of the foregoing, there is a needed for operational amplifiers that substantially eliminate input voltage offset errors, input bias current errors as well as provide a true rail-to-rail output while reducing output loading sensitivity.